LMK02000 Datasheet | Texas Instruments

Features - 1 20 fs Additive Jitter - Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 d Bc/Hz - Clock Output Frequency Range of 1 to 800 MHz - 3 LVDS and 5 LVPECL Clock Outputs - Dedicated Divider and Delay Blocks on Each Clock Output - Pin patible Family of Clocking Devices - 3.15 to 3.45 V Operation - Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm) 3 Description The LMK02000 precision clock conditioner bines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), three LVDS, and five LVPECL clock output distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system ponents. 2 Target Applications - Data Converter Clocking - Networking, SONET/SDH, DSLAM - Wireless Infrastructure - Medical - Test and Measurement - Military / Aerospace The clock conditioner es in a 48-pin WQFN package and is footprint patible with other clocking devices in the same family. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SNAS390D - NOVEMBER 2006 - REVISED SEPTEMBER 2007 3.1 Functional Block Diagram OSCin OSCin- Fin Distribution Path Fin- R Divider N Divider Phase Detector Charge Pump CLKout0 CLKout0- CLKout1 CLKout1- CLKout2 CLKout2- CLKout3 CLKout3-...