LMK00725 - Differential-to-3.3V LVPECL Fanout Buffer

Description

The LMK00725 is a low skew, high-performance clock fanout buffer which can distribute up to five 3.3V LVPECL outputs from one of two inputs, which can accept differential or single-ended inputs.

Features

1.
Five 3.3V Differential LVPECL Outputs.
Additive Jitter: 43 fs RMS (typ) @ 312.5 MHz.
Noise Floor (≥1 MHz offset): -158 dBc/Hz (typ) @ 312.5 MHz.
Output Frequency: 650 MHz (max).
Output Skew: 35 ps (max).
Part-to-Part Skew: 100 ps (max).
Propagation Delay: 0.37 ns (max).
Two Differential Input Pairs (pin-selectable).
CLKx, nCLK Input Pairs can accept LVPECL, LVDS, HCSL, SSTL, LVHSTL, or Single-Ended Signals.

Texas Instruments

📥 Download Datasheet

Datasheet Details

Part number	LMK00725
Manufacturer	Texas Instruments
File Size	1.18 MB
Description	Differential-to-3.3V LVPECL Fanout Buffer
Datasheet	LMK00725 Datasheet
Additional preview pages of the LMK00725 datasheet.

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Full PDF Text Transcription

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LMK00725 www.ti.com SNAS625A – SEPTEMBER 2013 – REVISED OCTOBER 2013 Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer Check for Samples: LMK00725 FEATURES 1 • Five 3.3V Differential LVPECL Outputs – Additive Jitter: 43 fs RMS (typ) @ 312.5 MHz – Noise Floor (≥1 MHz offset): -158 dBc/Hz (typ) @ 312.5 MHz – Output Frequency: 650 MHz (max) – Output Skew: 35 ps (max) – Part-to-Part Skew: 100 ps (max) – Propagation Delay: 0.37 ns (max) • Two Differential Input Pairs (pin-selectable) – CLKx, nCLK Input Pairs can accept LVPECL, LVDS, HCSL, SSTL, LVHSTL, or Single-Ended Signals • Synchronous Clock Enable • Power Supply: 3.

Published: Jul 2, 2023 |