DRA755 Datasheet | Texas Instruments

Overview 1.1 Features - Architecture designed for infotainment applications - Video, image, and graphics processing support - Full-HD video (1920 × 1080p, 60 fps) - Multiple video input and video output - 2D and 3D graphics - Dual Arm® Cortex®-A15 microprocessor subsystem - Up to two C66x floating-point VLIW DSP - Fully object-code patible with C67x and C64x+ - Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle - Up to 2.5MB of on-chip L3 RAM - Level 3 (L3) and level 4 (L4) interconnects - Two DDR2/DDR3/DDR3L memory interface (EMIF) modules - Supports up to DDR2-800 and DDR3-1066 - Up to 2GB supported per EMIF - Dual Arm® Cortex®-M4 Image Processing Units (IPU) - Up to two Embedded Vision Engines (EVEs) - IVA subsystem - Display subsystem - Display controller with DMA engine and up to three pipelines - HDMI™ encoder: HDMI 1.4a and DVI 1.0 pliant - Video Processing Engine (VPE) - 2D-graphics accelerator (BB2D) subsystem - Vivante® GC320 core - Dual-core Power VR® SGX544 3D GPU - Three Video Input Port (VIP) modules - Support for up to 10 multiplexed input ports - General-Purpose Memory Controller (GPMC) - Enhanced Direct Memory Access (EDMA) controller - 2-port gigabit ethernet (GMAC) - Sixteen 32-Bit general-purpose timers - 32-Bit MPU watchdog timer - Five Inter-Integrated Circuit ( I2C™) ports - HDQ™/ 1-Wire® interface - SATA interface - Media LB® (MLB)...