CY74FCT841T
description
The ’FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The ’FCT841T devices are buffered 10-bit-wide versions of the FCT373 function.
The ’FCT841T devices’ high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
NAME D LE Y OE
PIN DESCRIPTION
I/O DESCRIPTION
I Latch data inputs
Latch-enable input. The latches are transparent when LE is high. Input data is latched on the high-to-low transition.
O 3-state latch outputs
Output-enable...
