CDCUN1208LP Description
The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8.
CDCUN1208LP Key Features
- 1 Supports PCIe Gen1, Gen2, Gen3
- Configuration Options (Through Pins or SPI/I2C)
- Input Type (HCSL, LVDS, LVCMOS)
- Output Type (HCSL, LVDS, LVCMOS)
- Signal Edge Rate (Slow, Medium, Fast)
- Clock Input Divide Value (/1, /2, /4, /8)
- Low-Power Consumption and Power Management
- Integrated Voltage Regulators to Improve PSNR
- Excellent Additive Jitter Performance
- 200 fs RMS (10 kHz to 20 MHz), LVDS at