CDCLVP1204 Overview
Description
The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz.
Key Features
- 1 2:4 Differential Buffer
- Selectable Clock Inputs Through Control Terminal
- Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL
- Four LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 45 mA
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 450 ps
- Maximum Output Skew: 15 ps
- LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs
