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CDCLVP1204 - High-Performance Clock Buffer

General Description

The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications.

It has a maximum clock frequency up to 2 GHz.

Key Features

  • 1 2:4 Differential Buffer.
  • Selectable Clock Inputs Through Control Terminal.
  • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL.
  • Four LVPECL Outputs.
  • Maximum Clock Frequency: 2 GHz.
  • Maximum Core Current Consumption: 45 mA.
  • Very Low Additive Jitter:.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design CDCLVP1204 SCAS880F – AUGUST 2009 – REVISED SEPTEMBER 2015 CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer 1 Features •1 2:4 Differential Buffer • Selectable Clock Inputs Through Control Terminal • Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL • Four LVPECL Outputs • Maximum Clock Frequency: 2 GHz • Maximum Core Current Consumption: 45 mA • Very Low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz Offset Range: – 57 fs, RMS (typical) at 122.88 MHz – 48 fs, RMS (typical) at 156.25 MHz – 30 fs, RMS (typical) at 312.5 MHz • 2.375-V to 3.