Datasheet4U Logo Datasheet4U.com

CDCLVD1216 - 2:16 Low Additive Jitter LVDS Buffer

Description

The CDCLVD1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVDS clock outputs (OUT0, OUT15) with minimum skew for clock distribution.

The CDCLVD1216 can accept two clock sources into an input multiplexer.

Features

  • 1.
  • 2:16 Differential Buffer.
  • Low Additive Jitter:.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CDCLD080 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor
CDCLD100 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor
CDCLD120 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor
CDCLD200 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor
CDCLD400 SURFACE MOUNT SILICON CURRENT LIMITING DIODES Central Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
CDCLVD1212 2:12 Low Additive Jitter LVDS Buffer
CDCLVD1213 1:4 Low Additive Jitter LVDS Buffer
CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer
CDCLVD1208 2:8 Low Additive Jitter LVDS Buffer
CDCLVD110 PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CDCLVD1216 www.ti.com SCAS900B – OCTOBER 2010 – REVISED JANUARY 2011 2:16 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD1216 FEATURES 1 • 2:16 Differential Buffer • Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz • Low Output Skew of 55 ps (Max) • Universal Inputs Accept LVDS, LVPECL, LVCMOS • Selectable Clock Inputs Through Control Pin • 16 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible • Clock Frequency up to 800 MHz • 2.375–2.
Published: |