CDCL6010 Datasheet | Texas Instruments

FEATURES - 2 Single 1.8V Supply - High-Performance Clock Multiplier, Distributor, Jitter Cleaner, and Buffer With 11 Outputs - Low Output Jitter: 400fs RMS - Output Group Phase Adjustment - Low-Voltage Differential Signaling (LVDS) Input, 100Ω Differential On-Chip Termination, 30MHz to 319MHz Frequency Range - Differential Current Mode Logic (CML) Outputs, 50Ω Single-Ended On-Chip Termination, 15MHz to 1.25GHz Frequency Range - One Dedicated Differential CML Output, Straight PLL and Frequency Divider Bypass - Two Groups of Five Outputs Each with Independent Frequency Division Ratios; Optional PLL Bypass - Fully Integrated Voltage Controlled Oscillator (VCO); Supports Wide Output Frequency Range - Output Frequency Derived From VCO Frequency with Divide Ratios of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80 - Meets OBSAI RP1 v1.0 Standard and CPRI v2.0 Requirements - Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements - Integrated LC Oscillator Allows External Bandwidth Adjustment - PLL Lock Indication - Power Consumption: 640m W Typical - Output Enable Control for Each Output - SDA/SCL Device Management Interface - 48-pin QFN (RGZ) Package - Industrial Temperature Range: - 40°C to +85°C APPLICATIONS - Low Jitter Clocking for High-Speed SERDES - Jitter Cleaning of SERDES Reference Clocks for 1G/10G Ethernet, 1X/2X/4X/10X Fibre Channel, PCI Express, Serial ATA, SONET, CPRI, OBSAI, etc. - Up to 1-to-11 Clock Buffering and Fan-out 1 Bypass CML Output Differential LVDS Input 30MHz-319MHz PLL VCO SDA/SCL DIVIDER DIVIDER 5 Differential CML Outputs 15MHz-1.25GHz 5 Differential CML Outputs 15MHz-1.25GHz Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform...