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CDCDB2000 - 20-Output Clock Buffer

General Description

The CDCDB2000 is a 20-output LP-HCSL, DB2000QL compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-5, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces.

Key Features

  • 1 20 LP-HCSL outputs with integrated 85-Ω output terminations.
  • 8 hardware output enable (OE#) controls.
  • Additive phase jitter after DB2000QL filter: < 0.08ps rms.
  • Supports PCIe Gen 4 and Gen 5 Common Clock (CC) and Individual Reference (IR) architectures.
  • Spread spectrum-compatible.
  • Cycle-to-cycle jitter: < 50 ps.
  • Output-to-output skew: < 50 ps.
  • Input-to-output delay: < 3 ns.
  • 3.3-V core and IO supply voltages.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Order Now Technical Documents Tools & Software Support & Community CDCDB2000 SNAS787A – NOVEMBER 2019 – REVISED FEBRUARY 2020 CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5 1 Features •1 20 LP-HCSL outputs with integrated 85-Ω output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after DB2000QL filter: < 0.08ps rms • Supports PCIe Gen 4 and Gen 5 Common Clock (CC) and Individual Reference (IR) architectures – Spread spectrum-compatible • Cycle-to-cycle jitter: < 50 ps • Output-to-output skew: < 50 ps • Input-to-output delay: < 3 ns • 3.