CDC857-2 drivers equivalent, 2.5-/3.3-v phase-lock loop clock drivers.
D Distributes One Differential Clock Input to
Ten Differential Outputs
D External Feedback Pins (FBIN, FBIN) Are
Used t.
VCC 11 VCC 12 CLK 13
38 VCC 37 G
36 FBIN
The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the c.
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