CDC5806 Datasheet | Texas Instruments

FEATURES - High Performance Clock Generator - Clock Input patible With LVCMOS/LVTTL - Requires a 54-MHz Input Clock to Generate Multiple Output Frequencies - Low Jitter for Clock Distribution - Generates the Following Clocks: - VIDCLK 74.175824 MHz/54 MHz (Buffered) - AUDCLK 16.9344 MHz/12.288 MHz - CPUCLK 64 MHz - ASICCLK 32 MHz - USBCLK 48 MHz - MCCLK 38.4 MHz/19.2 MHz/12 MHz - Operates From Single 3.3-V Supply - Low Peak-to-Peak Period Jitter (150 ps Max) - PLLs Are Powered Down, if No Valid REF_IN Clock (< 5 MHz) is Detected or the VDD is Below 2 V - PLL Loop Filter ponents Integrated - Packaged in TSSOP (PW) 20-Pin Package - Industrial Temperature Range -40°C to 85°C Applications APPLICATIONS - Digital Television With a Memory Card Interface DESCRIPTION The CDC5806 is a clock generator which synthesizes video clocks, audio clocks, CPU clock, ASIC clock, USB clock, and a memory card clock from a 54-MHz system clock. Three phase-locked loops (PLLs) are used to generate the different frequencies from the system clock. On-chip loop filters and internal feedback eliminate the need for external ponents. Since the CDC5806 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLLs. The PLL stabilization time begins after the reference clock input has a stable phase and frequency. The device operates from a single 3.3-V supply voltage. The CDC5806 device is characterized for operation from -40°C to 85°C. PW PACKAGE (TOP VIEW) VIDSEL REF_IN PLL1VDD VIDCLK PLL1VSS PLL2VDD...