CDC3S04 Datasheet | Texas Instruments

FEATURES - 1:4 Low-Jitter Clock Buffer - Single-Ended Sine-Wave Clock Input and Outputs - Ultralow Phase Noise and Standby Current - Individual Clock Request Inputs for Each Output - On-Chip Low-Dropout Output (LDO) for Low- Noise TCXO Supply - Serial I2C Interface (patible With High- Speed Mode, 3.4 Mbit/s) - 1.8-V Device Power Supply - Wide Temperature Range, - 40°C to 85°C - ESD Protection: 2 KV HBM, 750 V CDM, and 100 V MM - Small 20-Pin Chip-Scale Package: 0.4-mm Pitch WCSP (1.6 mm × 2 mm) APPLICATIONS - Cellular Phones - Smart Phones - Mobile Handsets - Portable Systems - Wireless Modems Including GPS, WLAN, W- BT, D-TV, DVB-H, FM Radio, Wi MAX, and System Clock DESCRIPTION The CDC3S04 is a four-channel low-power low-jitter sine-wave clock buffer. It can be used to buffer a single master clock to multiple peripherals. The four sine-wave outputs (CLK1- CLK4) are designed for minimal channel-to-channel skew and ultralow additive output jitter. Each output has its own clock request inputs which enables the dedicated clock output. These clock requests are active-high (can also be changed to be active-low via I2C), and an output signal is generated that can be sent back to the master clock to request the clock (MCLK_REQ). MCKL_REQ is an opensource output and supports the wired-OR function (default mode). It needs an external pulldown resistor. MCKL_REQ can be changed to wired-AND or pushpull functionality via I2C. The CDC3S04 also provides an I2C interface (Hsmode) that can be used to enable or disable the outputs, select the polarity of the REQ inputs, and allow control of internal decoding. The CDC3S04 features an on-chip high-performance LDO that accepts voltages from 2.3 V to 5.5 V and outputs a 1.8-V supply. This 1.8-V supply can be used to power an external 1.8-V TCXO. It can be enabled or disabled for power saving at the TCXO. VBAT RESET MCLK_IN MCLK_REQ SCLH SDAH ADR_A0 VDD_DIG VDD_ANA Reset I2C Control Register VLDO REQ1 CLK1 REQ2 CLK2 REQ3...