CDC3RL02 Datasheet | Texas Instruments

Features - Low Additive Noise: - - 149 d Bc/Hz at 10-k Hz Offset Phase Noise - 0.37 ps (RMS) Output Jitter - Limited Output Slew Rate for EMI Reduction (1- to 5-ns Rise/Fall Time for 10-p F to 50-p F Loads) - Adaptive Output Stage Controls Reflection - Regulated 1.8-V Externally Available I/O Supply - Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP (0.8 mm × 1.6 mm) - ESD Performance Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 1000-V Charged-Device Model (JESD22-C101-A Level III) 2 Applications - Cellular Phones - Global Positioning Systems (GPS) - Wireless LAN - FM Radio - Wi MAX - W-BT VBATT VLDO VCC EN CLK_OUT1 CLK_REQ1 MCLK_IN VCC EN CLK_OUT2 CLK_REQ2 Switch/ Decoder Copyright © 2017, Texas Instruments Incorporated Simplified Block Diagram 3 Description The CDC3RL02 is a two-channel clock fan-out buffer and is ideal for use in portable end-equipment, such as mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities. It buffers a single master clock, such as a temperature pensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each of which enable a single clock output. The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3-V signal (peak-topeak). CDC3RL02 has been designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3 V to 5.5 V and outputs 1.8 V, 50 m A. This 1.8-V supply is externally available to provide regulated power to...