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CD74HCT73 - Dual J-K Flip-Flop

Download the CD74HCT73 datasheet PDF. This datasheet also covers the CD74HC73 variant, as both devices belong to the same dual j-k flip-flop family and are provided as variant models within a single manufacturer datasheet.

Description

Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times Asynchronous Reset Complementary Outputs Buffered Inputs TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, Fanout (Over Temperature Range) - St

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Note: The manufacturer provides a single datasheet file (CD74HC73-etcTI.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Data sheet acquired from Harris Semiconductor SCHS134E February 1998 - Revised September 2003 CD54HC73, CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC73, CD74 HCT73 ) /Subject (Dual J-K FlipFlop Features Description • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF, • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . .