* LSTTL input logic compatible
  – VIL(max) = 0.8 V, VIH(min) = 2 V
* CMOS input logic compatible
  – II ≤ 1 µA at VOL, VOH
* Buff.

* Alarm / tamper detect circuit
* S-R latch 3 Description This device contains three independent 3-input NAND .

This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y = A
* B
* C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HCT10M SOIC (14) 8.70 mm × 3.90 mm CD74.

CD74HCT10

CD74HCT107

CD74HCT109

CD74HCT10M

CD74HCT11

CD74HCT112

CD74HCT123

CD74HCT123E

CD74HCT123M

CD74HCT125

CD74HCT126

CD74HCT132

CD74HCT132E

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