CD74AC238
Overview
- 5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
- Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
- Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
- Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception
- Balanced Propagation Delays D ±24-mA Output Drive Current - Fanout to 15 F Devices
- SCR-Latchup-Resistant CMOS Process and Circuit Design
- Exceeds 2-kV ESD Protection Per
