Datasheet Details
| Part number | CD54ACT112 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 910.90 KB |
| Description | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS |
| Datasheet | CD54ACT112-etcTI.pdf |
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Overview: CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current – Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54ACT112 . . . F PACKAGE CD74ACT112 . . .
| Part number | CD54ACT112 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 910.90 KB |
| Description | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS |
| Datasheet | CD54ACT112-etcTI.pdf |
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/ordering information The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK).
Compare CD54ACT112 distributor prices and check real-time stock availability from major suppliers. Prices and inventory may vary by region and order quantity.
| Part Number | Description |
|---|---|
| CD54ACT109 | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS |
| CD54ACT138 | 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS |
| CD54ACT139 | DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS |
| CD54ACT151 | 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS |
| CD54ACT153 | DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS |
| CD54ACT161 | 4-BIT SYNCHRONOUS BINARY COUNTERS |
| CD54ACT163 | 4-BIT SYNCHRONOUS BINARY COUNTERS |
| CD54ACT164 | 8-Bit Serial-In/Parallel-Out Shift Register |
| CD54ACT174 | HEX D-TYPE FLIP-FLOPS |
| CD54ACT191 | Presettable Synchronous 4-Bit Binary Up/Down Counter |