Datasheet Summary
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SLOS755
- DECEMBER 2012
12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface
Check for Samples: ADS61JB23
Features
- Output Interface:
- Single-Lane and Dual-Lane Interfaces
- Maximum Data Rate of 1.6 Gbps
- Meets JESD204A Specification
- CML Outputs with Current Programmable from 2 mA
- 32 mA
- Power Dissipation:
- 440 mW at 80 MSPS in Single Lane Mode
- Power Scales Down with Clock Rate
- Input Interface: Buffered Analog Inputs
- 71.7 dBFS SNR at 70 MHz IF
- Analog Input FSR: 2 Vpp
- External and Internal (trimmed) Reference
Support
- 1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
- Programmable Digital Gain: 0dB
- 6dB
- Straight...