ADS5525 Datasheet | Texas Instruments

.ti. SLWS191B - JULY 2006 - REVISED MAY 2007 12-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Features - Maximum Sample Rate: 170 MSPS - 12-Bit Resolution - No Missing Codes - Total Power Dissipation 1.1 W - Internal Sample and Hold - 70.5-d BFS SNR at 70-MHz IF - 84-d Bc SFDR at 70-MHz IF - 11 bits ENOB Minimum at 70-MHz IF - Double Data Rate (DDR) LVDS and Parallel CMOS Output Options - Programmable Gain up to 6 d B for SNR/SFDR Trade-Off at High IF - Reduced Power Modes at Lower Sample Rates - Supports input clock amplitude down to 400 m VPP - Clock Duty Cycle Stabilizer - No External Reference Decoupling Required - Internal and External Reference Support - Programmable Output Clock position to ease data capture - 3.3-V Analog and Digital Supply - 48-QFN Package (7 mm × 7 mm) APPLICATIONS - Wireless munications Infrastructure - Software Defined Radio - Power Amplifier Linearization -...