ADC32RF80 Datasheet | Texas Instruments

Features - 1 14-Bit, Dual-Channel, 3-GSPS ADC - Noise Floor: - 155 d BFS/Hz - RF Input Supports Up to 4.0 GHz - Aperture Jitter: 90 f S - Channel Isolation: 95 d B at f IN = 1.8 GHz - Spectral Performance (f IN = 900 MHz, - 2 d BFS): - SNR: 60.1 d BFS - SFDR: 66-d Bc HD2, HD3 - SFDR: 76-d Bc Worst Spur - Spectral Performance (f IN = 1.85 GHz, - 2 d BFS): - SNR: 58.9 d BFS - SFDR: 67-d Bc HD2, HD3 - SFDR: 76-d Bc Worst Spur - On-Chip Digital Down-Converters: - Up to 4 DDCs (Dual-Band Mode) - Up to 3 Independent NCOs per DDC - On-Chip Input Clamp for Overvoltage Protection - Programmable On-Chip Power Detectors with Alarm Pins for AGC Support - On-Chip Dither - On-Chip Input Termination - Input Full-Scale: 1.35 VPP - Support for Multi-Chip Synchronization - JESD204B Interface: - Subclass 1-Based Deterministic Latency - 4 Lanes Per Channel at 12.5 Gbps - Power Dissipation: 3.2 W/Ch at 3.0 GSPS - 72-Pin VQFN Package (10 mm × 10 mm) 2 Applications - Multi-Carrier GSM Cellular Infrastructure Base Stations - Telemunications Receivers - DPD Observation Receivers - Backhaul Receivers - RF Repeaters and Distributed Antenna Systems 3 Description The ADC32RF8x (ADC32RF80 and ADC32RF83) is a 14-bit, 3-GSPS, dual-channel tele receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF8x family delivers a noise spectral density of - 155 d BFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch...