ADC31JB68
Features
- 1 Single Channel
- 16-Bit Resolution
- Maximum Clock Rate: 500 Msps
- Small 40-Pin QFN Package (6 x 6 mm)
- Input Buffer Input Bandwidth (3 d B): 1300 MHz
- Aperture Jitter: 80 fs
- On Chip Clock Divider: /1, /2, /4
- On Chip Dither
- Consistent Dynamic Performance Using
Foreground and Background Calibration
- Input Amplitude and Phase Adjustment
- Input Full Scale: 1.7 Vpp
- Power Supplies: 1.2/1.8/3 V
- JESD204B Interface
- Subclass 1 pliant
- 2 Lanes at 5 Gbps
- Support for Multi-chip Synchronization
- Key Specifications
- Power Dissipation: 915 m W at 500 Msps
- Performance at fin = 210 MHz at
- 1 d BFS
- SNR: 69.3 d BFS
- NSD:
- 153.3 d BFS/Hz
- SFDR: 80 d Bc
- Non-HD2,HD3:
- 91 d BFS
- Performance at fin = 450 MHz at
- 1 d BFS
- SNR: 67 d BFS
- NSD:
- 151 d BFS/Hz
- SFDR: 77 d Bc HD2,3
- Non-HD2,HD3:
- 89 d BFS
Transmitted Eye at Output of 18-Inch, 5-mil. FR4 Microstrip Trace at 5 Gb/s
With Optimized De-Emphasis
2...
