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• Inputs Are TTL-Voltage Compatible • Provides Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
• EPIC™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Ceramic 300-mil
DIPs
description
54ACT11821, 74ACT11821 10-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS156A – NOVEMBER 1990 – REVISED APRIL 1993
54ACT11821 . . . JT PACKAGE 74ACT11821 . . .