74ACT11139 Datasheet | Texas Instruments

74ACT11139 DUAL 2ĆLINE TO 4ĆLINE DECODER/DEMULTIPLEXER D Inputs Are TTL-Voltage patible D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems D Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception D Fully Synchronous Operation for Counting D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise D EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-m A Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N) SCAS175A - SEPTEMBER 1991 - REVISED APRIL 1996 D, N, OR PW PACKAGE (TOP VIEW) 1Y1 1 1Y2 2 1Y3 3 GND 4 2Y0 5 2Y1 6 2Y2 7 2Y3 8 16 1Y0 15 1A 14 1B 13 1G 12 VCC 11 2G 10 2A 9 2B description The 74ACT11139 is designed for use in high-performance memory-decoding or data-routing applications that require very short propagation delay times. In high-performance memory systems, this decoder is used to minimize the effects of system decoding. The 74ACT11139 is posed of two individual 2-line to 4-line decoders in a single package. The active-low enables (1G or 2G) can be used as data lines in demultiplexing applications. This decoder/demultiplexer Features fully buffered inputs, each of which represents only one normalized load to its driving circuit. The 74ACT11139 is characterized for operation from - 40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS G B A Y0 Y1 Y2 Y3 HXXHHHH L L L LHHH L...