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ą 54AC11238, 74AC11238 3ĆLINE TO 8ĆLINE DECODERS/DEMULTIPLEXERS ą
SCAS039A − APRIL 1988 − REVISED APRIL 1993
• Designed Specifically for High-Speed
54AC11238 . . . J PACKAGE
Memory Decoders and Data Transmission
74AC11238 . . . D OR N PACKAGE
Systems
(TOP VIEW)
• Noninverting Version of ′AC11138 • Incorporates 3 Enable Inputs to Simplify
Cascading and/or Data Reception
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
• EPICt (Enhanced-Performance Implanted
Y1 Y2 Y3 GND Y4 Y5 Y6 Y7
1 2 3 4 5 6 7 8
16 Y0 15 A 14 B 13 C 12 VCC 11 G1 10 G2A 9 G2B
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
54AC11238 . . .
74AC11238 Datasheet
