900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Zarlink Semiconductor

CLA80000 Datasheet Preview

CLA80000 Datasheet

High Density CMOS Gate Arrays

No Preview Available !

( DataSheet : www.DataSheet4U.com )
CLA80000 Series
High Density CMOS Gate Arrays
INTRODUCTION
The CLA80k gate array series from Zarlink Semiconductor
offers advantages in speed and density over previous array
series. Improvements in design combined with advances in
simulation accuracy allow the implementation of complex
systems in excess of 260,000 gates.
FEATURES
I 0.7µ (0.8µ drawn) process
I Typical gate delay 210ps
I Accurate simulation delay (multi platform support)
I Support for industry standard workstations
I Comprehensive cell library
I 3V option for low power operation
I Split rail operation (optional 5V I/O, 3V core logic)
I Low skew clock distribution strategy
I Power and ground distribution grids
I Extensive range of package options
OVERVIEW
The gate array has a comprehensive cell library including
RAM generators as well as JTAG circuits. CLA80k is Zarlink
Semiconductor’s seventh generation CMOS gate array
product. The family consists of 22 arrays implemented on a
proven 0.7µm (0.8µm drawn) process which offers two or
three layer metal.
Zarlink Semiconductor’s Design Centres offer support on a
variety of design routes customized to individual
requirements.
Zarlink supplies design kits for the major industry standard
ASIC design tools and all kits support advanced nonlinear
delay calculations essential for accurate simulation.
Standard Density Pad Arrays are targeted for use in
ceramic packaging and for those applications which require
assembly in conformance with MIL STD 883.
DS3820
ISSUE 2.1
July 1997
ARRAY SIZES
The CLA80k series comprises 9 base arrays and 22
variants ranging from 2816 to 513,136 array elements. The
optimum array for your requirement may be selected from
the tables below.
Double Layer Metal Arrays (High Density Pads)
Array type
CLA81XXX
CLA82XXX
CLA83XXX
CLA84XXX
CLA85XXX
CLA86XXX
CLA87XXX
Array
Usable
elements gates
Total
Pads
2816
1400 64
8736
4260 88
17920
8400 112
30784
13600 136
54720
22000 168
100048
30000 216
157872
48000 264
Triple Layer Metal Arrays (High Density Pads)
Array type
CLT81XXX
CLT82XXX
CLT83XXX
CLT84XXX
CLT85XXX
CLT86XXX
CLT87XXX
CLT88XXX
CLT89XXX
Array
Usable
elements gates
Total
pads
2816
1680 64
8736
5200 88
17920
10700 112
30784
18000 136
54720
32500 168
100048
58000 216
157872
90000 264
307568 170000 360
513136 260000 456
Standard Density Pad Arrays
Array type
MLA85XXX
MLT85XXX
MLA87XXX
MLT87XXX
MLT88XXX
MLT89XXX
Array
Usable
elements gates
Total
pads
54720
22000 144
54720
32500 144
157872
48000 232
157872
90000 232
307568 170000 312
513136 260000 384
www.DataSheet4U.com
www.DataSheet4U.com




Zarlink Semiconductor

CLA80000 Datasheet Preview

CLA80000 Datasheet

High Density CMOS Gate Arrays

No Preview Available !

ARCHITECTURE
Core cell
I Optimized structure for a variety of logic elements
I Allows routing through cells for compact layout
The basic unit from which all library functions are
constructed is called an ‘array element’. An array element
consists of two P-channel and two N-channel plus a small
P-channel transistor. Two basic cell or array elements are
illustrated in Figure 1. To achieve the required circuit
function, logic designers use a set of cells. Each library
component realizes a logic function, ranging in complexity
from an inverter to a master-slave ‘D’ flip-flop. A fixed metal
interconnection of the transistors from one or more array
elements implements the cell function. A design is
specified in terms of cells, macros, modules and their
interconnections, which are then simulated using one of the
many supported design platforms.
If a design uses only two layers of metal then a set of four
masks is required. One for contacts, one for vias
(connections between the metal layers) and two for metals.
If a design uses three layer metal then six masks are
required. One for contacts, two for vias and three for
metals.
I/O ARRANGEMENT
I High density and standard density pads available
I 4KV ESD and latchup immunity
I Programmable slew rate control
Around the outside of the array are I/O blocks and pads
placed at the chip periphery. All arrays have wide power
bus rings situated over the I/O blocks. The partition of the
I/O cell is shown in Figure 2. For high density pad arrays
three pads are placed every four I/O cells whilst for
standard density array pads two pads are placed for every
three I/O cells.
Each I/O cell is divided into a number of sections allowing
a wide variety of different I/O cells to be constructed. Each
I/O block can be customized as an input, output or bi-
directional I/O port. In addition any pad location can be
used as a positive or negative supply pad.
Electrostatic discharge protection (ESD) is built into the I/O
cells. This protection can withstand in excess of 4kV. The
structure is also highly resistant to latch-up due to the
epitaxial substrate used in the process.
Slew rate control is provided within the I/O cell structure to
minimize supply noise transients. This is a useful feature in
larger designs where multiple high drive outputs need to be
switched simultaneously.
2
VDD Supply
P Trans
Shared
Diffusion
N Trans
GND Supply
Array Element Array Element
Figure 1 Pair of array elements
IB-VDD
IB-GND
OP-VDD
OP-GND
Intermediate
Buffers
Output
Drivers
Bond
Pads
OP-VDD
Repeated Structure
Figure 2 High density pad spacing


Part Number CLA80000
Description High Density CMOS Gate Arrays
Maker Zarlink Semiconductor
PDF Download

CLA80000 Datasheet PDF






Similar Datasheet

1 CLA80000 High Density CMOS Gate Arrays
Zarlink Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy