CLA70000 Datasheet | Zarlink Semiconductor

Overview The CLA70000 gate array family is Zarlink Semiconductors' sixth generation CMOS gate array product. The family consists of nine arrays implemented on the latest generation (1 micron) twin well epitaxial CMOS process. The process in conjunction with the advanced layout and route software, offers extremely high packing densities. The array architecture is based upon the earlier well proven CLA60000 series with the emphasis being placed on high speed, high packing density, and provision of prehensive cell libraries. The cell libraries enpass new DSP and other specialized macros. Full design support is available for major industry standard ASIC design software tools, as well as Zarlink Semiconductor’s proprietary PDS2 design environment. Design support is provided by Zarlink Semiconductor’s design centers, each offering a variety of design routes, which may be customized to individual customer requirements. Features - - - - Low power channelless arrays from 5,000 to 250,000 available gates (5µ W / gate / MHz) 1 micron (0.8 micron effective) twin well epitaxial process Typical gate delays of 400 ps (NAND2 , Fanout=2) prehensive cell library including DSP, JTAG/BIST and piled memory cells (ROM blocks to 64K bits and RAM blocks to 16K bits) Extensive Range of Plastic and Ceramic Packages for both Surface Mount and Through Board Assembly Flexible I/O structure allows user to define power pad locations Fully supported on industry standard workstations and in-house software High drive output stages with slew rate control Supports JTAG and BIST test philosophies (IEEE 1149-1 Test Procedures) MIL 883C pliant product available (paragraph 1.2.1) - - - - - - Product Details The CLA70000 array series is shown below with typical figures given for usable gates. Actual gate utilization is dependent on circuit structure, giving a range of 40 -70% for two layer metallisation. DEVICE NUMBER CLA70000 CLA71000 CLA72000 CLA73000 CLA74000 CLA75000 CLA76000 CLA77000...