900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






Zarlink Semiconductor

CLA70000 Datasheet Preview

CLA70000 Datasheet

High Density CMOS Gate Arrays

No Preview Available !

( DataSheet : www.DataSheet4U.com )
CLA70000 Series
High Density CMOS Gate Arrays
Recent advances in CMOS processing technology and
improvements in design architecture have led to the
development of a new generation of array-based ASIC
products with vastly improved gate integration densities. This
family of CLA70000 1 micron CMOS arrays brings
considerable advantages to the design of next generation
systems combining high performance and high complexity.
Features
• Low power channelless arrays from 5,000 to 250,000
available gates (5µW / gate / MHz)
• 1 micron (0.8 micron effective) twin well epitaxial process
• Typical gate delays of 400 ps (NAND2 , Fanout=2)
• Comprehensive cell library including DSP, JTAG/BIST
and compiled memory cells (ROM blocks to 64K bits
and RAM blocks to 16K bits)
• Extensive Range of Plastic and Ceramic Packages for
both Surface Mount and Through Board Assembly
• Flexible I/O structure allows user to define power pad
locations
• Fully supported on industry standard workstations and
in-house software
• High drive output stages with slew rate control
• Supports JTAG and BIST test philosophies (IEEE 1149-1
Test Procedures)
• MIL 883C compliant product available (paragraph 1.2.1)
DS2462
ISSUE 3.1
March 1992
Overview
The CLA70000 gate array family is Zarlink
Semiconductors' sixth generation CMOS gate array product.
The family consists of nine arrays implemented on the latest
generation (1 micron) twin well epitaxial CMOS process. The
process in conjunction with the advanced layout and route
software, offers extremely high packing densities.
The array architecture is based upon the earlier well
proven CLA60000 series with the emphasis being placed on
high speed, high packing density, and provision of
comprehensive cell libraries. The cell libraries encompass
new DSP and other specialized macros.
Full design support is available for major industry standard
ASIC design software tools, as well as Zarlink
Semiconductor’s proprietary PDS2 design environment.
Design support is provided by Zarlink Semiconductor’s
design centers, each offering a variety of design routes, which
may be customized to individual customer requirements.
Product Details
The CLA70000 array series is shown below with typical
figures given for usable gates. Actual gate utilization is
dependent on circuit structure, giving a range of 40 -70% for
two layer metallisation.
DEVICE
NUMBER
CLA70000
CLA71000
CLA72000
CLA73000
CLA74000
CLA75000
CLA76000
CLA77000
CLA78000
I/O AND
POWER PADS
44
68
84
100
120
160
200
256
304
GATE
COMPLEXITY
5K
12K
19K
27K
39K
70K
110K
182K
256K
ESTIMATED
USABLE GATES
2.5K
6K
9.5K
13.5K
17.5K
31.5K
49.5K
82K
115K
www.DataSheet4U.com
www.DataSheet4U.com




Zarlink Semiconductor

CLA70000 Datasheet Preview

CLA70000 Datasheet

High Density CMOS Gate Arrays

No Preview Available !

CLA70000 Series
Core Cell Arrangement
• Supports compact macros
• Allows high density routing
A four transistor group (2 NMOS and 2 PMOS) (fig.1)
forms the basic cell of the core array. This array element is
repeated in a regular fashion over the complete core area to
give an homogenous ‘Full Field’ (sea of gates) array. This
lends itself to hierarchical design, allowing pre-routed user
defined subcircuits to be repeated anywhere on the array. The
core cell structure together with all associated cell libraries
have been carefully designed to maximize the number of nets
which may be routed through the cell. This enables optimal
routing of both data flow and control signal distribution
schemes thus giving very high overall utilization factors. This
feature is of particular benefit in designs using highly
structured blocks such as memory or arithmetic functions.
I/O Buffer Arrangement
• Several hundred different I/O cell combinations
• Programmable Slew rate Control on all Outputs
• Excellent Latchup and ESD immunity
The I/O buffers are the interface to external circuitry and
are therefore required to be robust and flexible. Both inputs
and outputs incorporate electrostatic discharge (ESD)
protection structures which can withstand in excess of 2KV,
and are highly resistant to latch-up due to the epitaxial
process. In addition the construction concepts used for the
I/O cells provide the designer with several hundred different
options of I/O cell configuration.
The CLA70000 I/O buffers (fig.2) contain all the
components for static protection, CMOS and TTL compatible
input stages, and a wide variety of intermediate and output
drive configurations. Included are Schmitt triggers, tristate
VVSDSD
SSuupppplyly
Programmable
contacts
VVSSSS
SSuupppplyly
Figure 1 - Diagrammatic representation of Array Core Cell
controls, and slew rate controlled output buffers. All I/O buffer
locations can be configured as supply pads (VDD and VSS).
Slew rate control of output drivers is a useful feature when
multiple high drive outputs need to be switched
simultaneously, as may occur on driving capacitive loads
such as buses. Using regular output buffers with their
inherently fast edge speed can lead to significant power
supply noise transients, with possible mis-operation as a
result. To overcome this problem. The CLA70000 family
includes a set of slew rate controlled output drivers, which use
proprietary design techniques to control the turn-on of the
output transistors (di/dt). These cells provide a significant
benefit in the trade off between switching current magnitude
and the number of supply pads required.
SLEW RATE CONTROL
I/O BLOCK
INPUT
DATA
2.5 Volts
slew rate
D controlled
driver
P
N
P
OPT3
N
PIN
50 pF
2.5 Volts
IBSK1, IBSK2 and IBSK3 have been characterised
to give the correct timing when connected to the OPT* cells.
Fig 2. Slew Control & I/O Block
IB1 IB2 IB3 IB4 IB5
OP1
IP
OP2
Bonding
Pad
I/O BLOCK
2


Part Number CLA70000
Description High Density CMOS Gate Arrays
Maker Zarlink Semiconductor
PDF Download

CLA70000 Datasheet PDF






Similar Datasheet

1 CLA70000 High Density CMOS Gate Arrays
Zarlink Semiconductor





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z



Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy