UD61466 - DRAM

Name: UD61466
SKU: UD61466-573633

ZMD

Datasheet Details

meanwhile LOW leads to a Write cycle.

UD61466 64K x 4 DRAM SCM facilitates faster data operation with predefined row address. Via 8 address inputs the 16 address bits are transmitted into the internal address memories in a time-multiplex operation. The falling RASedge takes over the row address. After the row address hold time the column address can be applied. During the Read cycle the address transfer is not latched by the falling edge at the CAS input, so that the column address must be applied until the data are valid at the ou.

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Published: Mar 6, 2007 |