XCV600 - Virtex Field Programmable Gate Array

This page provides the datasheet information for the XCV600, a member of the XCV800 Virtex Field Programmable Gate Array family.

Datasheet Summary

Description

The Virtex FPGA family delivers high-performance, high-capacity programmable logic solutions.

Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 µm CMOS process.

Features

Fast, high-density Field-Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant - Hot-swappable for Compact PCI Multi-standard SelectIO™ interfaces - 16 high-performance interface standards - Connects directly to ZBTRAM devices Built-in clock-management circuitry - Four dedicated delay-locked loops (DLLs) for advanced clock control - Four primary low-skew global clock distribution nets, plus 24 secondary local clock ne.

Xilinx

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Datasheet Details

Part number	XCV600
Manufacturer	Xilinx
File Size	593.82 KB
Description	Virtex Field Programmable Gate Array
Datasheet	XCV600 Datasheet
Additional preview pages of the XCV600 datasheet.

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Full PDF Text Transcription

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0 R Virtex™ 2.5 V www.DataSheet4U.com Field Programmable Gate Arrays 0 0 DS003-1 (v2.

Published: May 1, 2010 |