XC7Z007S Datasheet

Features and Benefits

timers
• One global timer
• Two triple-timer counters Caches
• 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU)
• 512 KB 8-way set-associative Level 2 cache (shared between the CPUs)
• Byte-parity support On-Chip Memory
• On-chip boot ROM
• 256 KB on-chip RA.