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PC97551 Datasheet Preview

PC97551 Datasheet

Embedded Controller

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Product Brief
February 2006
Revision 1.1
PC97551
Embedded Controller for Notebook Systems
General Description
The Winbond PC97551 is an embedded controller (EC) for
mainstream notebook applications. It includes a highly opti-
mized set of functions, which provide a hardware/firmware
partition that enables the implementation of flexible solu-
tions; and its high-performance CPU core enables EC func-
tionality to be extended via the firmware.
The PC97551 incorporates National’s CompactRISCCR16B
core (a high-performance 16-bit RISC processor), internal
ROM and RAM memories, system support functions and a
Bus Interface Unit (BIU) that directly interfaces with both ex-
ternal memory (such as flash) and I/O devices.
System support functions include: watchdog, PWM, timers,
interrupt control, General-Purpose I/O (GPIO) with internal
keyboard matrix scanning, PS/2® Interface, SMBus® inter-
face, analog-to-digital (ADC) and digital-to-analog (DAC)
converters for battery charging circuitry, system monitoring
and analog controls.
The PC97551 interfaces with the host via an LPC interface
that provides the host with access to the Keyboard and em-
bedded controller interface channels and to the BIOS flash.
Like other members of Winbond’s Advanced I/O family, the
PC97551 is PC01 and ACPI compliant.
Outstanding Features
Host interface, based on Intel’s LPC Interface Specifi-
cation Revision 1.1, August 2002
PC2001 Rev 1.0, and ACPI 3.0 compliant
16-bit RISC core, with 2 Mbytes address space, run-
ning at up to 20 MHz
Shared BIOS flash memory (external)
92 GPIO ports (including keyboard scanning) with a
variety of wake-up events
JTAG-based debugger interface
Software and hardware controlled clock throttling and
extremely low current consumption in Idle mode
176-pin LQFP and FBGA packages
System Block Diagram
South Bridge
Display
Keyboard Mouse Touch Touch
Pad Point
SuperI/O
LPC
PWBTN
ECSCI Sleep ON
PWUREQ State Control
SMI
Lid
Switch Brightness
Contrast
On/Off
4x
PS/2
Keyboard Scan
Internal
Keyboard
PCI TPM
PCI
Devices
& Boards
JTAG
Wake-Up
Enable
Development
PWM
Tacho
PC97551
Embedded Controller
for Notebook Systems
Switch Pad
System Control and LEDs
and Status
Beep
Power Switch
Speaker
Shared Flash Memory
EC Firmware,
System BIOS
Local Bus
DDrDvrrv.v
Voltage
Current
CPU
Fans
Temperature
AC
Detect
ON and
Switch
Control
Voltage
Current
Control Direct CD
Voltage
Temp.
Player
2x
SMBus
Power
Supply
Charger
Battery
Input Output
Port Port
Expansion GPIOs
AC Adaptor
Temp.
Sensor
E2PROM Docking
© 2006 Winbond Electronics Corporation
www.winbond.com




Winbond Electronics

PC97551 Datasheet Preview

PC97551 Datasheet

Embedded Controller

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PC97551 Block Diagram
LPC Serial
I/F IRQ SMI
Reset &
Config
CR16B Core
Processing
Unit
Host
Controlled
Functions
LPC Bus I/F
Internal Bus
Core Bus
I/F Functions
CR Access Shared mem. Bus
Bridge + Protection Adapter
Memory
RAM
ROM
Peripheral Bus
Peripherals
DMA
BIU
KBC + PM
Host I/F
MSWC
HFCG
ICU
KBSCAN
GPIO
ACB
(X2)
Timer +
WDG
ADC
USART
Valid Battery
+ Oscillator
PMC MIWU
CLK
32.768 KHz
Debugger
I/F
PS/2
I/F
MFT16
(X2)
PWM
DAC
JTAG
External
Memory + I/O
Features
Embedded Controller
CompactRISC CR16B Processing Unit - a 16-bit em-
bedded RISC processor core (the “core”)
Internal Memory
Boot block for core code in 4 Kbytes of ROM
4 Kbytes of on-chip RAM with contents protection
ROM and RAM both can hold code and data
Bus Interface Unit (BIU) supporting:
Up to 2 Mbytes for code and data
Provides two chip-selects for flash/ROM and SRAM
devices
Provides one chip-select for I/O devices
8- or 16-bit wide bus
Configurable wait states
Enhanced performance using fast read cycles
Single-cycle, fast-read (word-aligned)
Two-byte, burst-read (byte-aligned)
BIOS sharing with PC host
Host-core shared memory access protection
Host-controlled with core override
64-Kbyte and 8-Kbyte blocks with independent
protection
Hardware-protected boot zone for host code
Download for on-board code updating
Host-controlled via LPC
Core-controlled via JTAG or serial port
External memory “power-down” mode
Operation Modes
IRE - Normal operation mode
OBD - On-Board Development mode
Used for development in the final system
Communicates with debugger via JTAG interface
Hardware breakpoint support
DEV - Development mode
Used in In-System Emulators (ISE) and Applica-
tion Development Boards (ADB)
Communicates with debugger via JTAG interface
On-chip ROM is replaced with off-chip SRAM
Cycle-by-cycle compatible with IRE mode
LPC System Interface
8-bit I/O and 8-bit memory read and write cycles
8-bit FWH read and write with wait-sync cycles
Bootable memory support
Base Address (BADDR) strap to determine the base
address of the Index-Data register pair
Serial IRQ (SERIRQ) support
LPCPD and CLKRUN support
Core-Controlled Functions
Interrupt Control Unit (ICU)
Non-maskable interrupt input (PFAIL)
31 maskable vectored interrupts
Enable and pending indication for each interrupt
General-purpose external interrupt inputs through
MIWU
www.winbond.com
2
Revision 1.1


Part Number PC97551
Description Embedded Controller
Maker Winbond Electronics
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