A2V56S40DTP-7PP sdram equivalent, 256mb sdram.
ITEM
tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle Time (Min.) CL=2 CL=3
-6
6 42 CL=2 CL=3 V56S20 15 5 60 100 110 130 3
A2V56S20/30/40BTP -7E -7 -75 -8
7 7 45 20 5.4 5.4 63 .
(4-BANK x 16,777,216-WORD x 4-BIT) (4-BANK x 8,388,6084-WORD x 8-BIT) (4-BANK x 4,194,304-WORD x 16-BIT)
A2V56S20BTP is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and A2V56S30BTP is organized as 4-bank x 8,3.
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