TXC-05810 Datasheet | Transwitch

ATURES - Tran Switch Cell Bus switch fabric pliant, interoperable with CUBIT-Pro (TXC-05802 and TXC-05802B) and CUBIT-3 (TXC-05804) RISC-based hardware architecture Dual independent Cell Bus interfaces for increased throughput or redundancy UTOPIA Level 2P interface (ATM/PHY layer emulation for cell and packet transport) Support for local host with capability for Cell Bus based management 32-/64-bit synchronous SRAM port for data storage Upgradeable firmware supports design and field upgrades Cell insertion/extraction through host interface Message-based interface for host-ASPEN munication Operates at bit rates up to 155 Mbit/s ASPEN Device DESCRIPTION The ASPEN device (TXC-05810) is a revolutionary, RISC-based processor designed to support the requirements of next generation multi-service access systems. The ASPEN supports Cell Bus operation in both cell and packet modes via two independent Cell Bus ports. The ASPEN and Cell Bus may be configured to support redundant system operation or, alternatively, to provide greater system throughput. Line interface is via UTOPIA Level 2 for ATM cells or Level 2P for variable length packets. Buffering of data traffic and control information, such as connection tables, is stored in an external synchronous SRAM. munication to a local host, if desired, is message based and via an external Dual Port RAM. The flexible nature of the ASPEN device architecture supports a variety of cell, packet, and cell/packet interworking modes. The ASPEN device’s mode of operation is determined by firmware downloaded into the device instruction memory. Contact Tran Switch for details of UTOPIA Level 2P interface specifications and information on available operational firmware. - - - - - - - - - - APPLICATIONS Data Shee - - . - ATM Access Multiplexers +3.3 V ±5% and +2.5 V ±5% power supplies for - DSLAM Applications input/output and CMOS core circuits, - Multi-Service Access Multiplexers respectively - ATM LAN Switch Test Access Port for IEEE...