The following content is an automatically extracted verbatim text
from the original manufacturer datasheet and is provided for reference purposes only.
View original datasheet text
• Detect and generate DS3 AIS, and idle signals • Transmit reference generator for serial operation • Transmit and receive Far End Alarm and Control (FEAC) with double word capability and automatic transmission • Maskable hardware interrupt for eight alarms
• Transmit single errors: framing, FEBE, C-bit parity, and P-bit parity • FEBE, C-bit, and P-bit performance counters • Counters for F-bit and M-bit errors
• Counter for coding violations and excessive zeros • Transmit-to-Receive and Receive-to-Transmit loopbacks • Outputs can be set to high-impedance state • Selectable mode for TXC-03401 emulation • Single +5 volt power supply
• Available as 68-pin plastic leaded chip carrier or 80-pin thin plastic quad flat package (TQFP)
LINE SIDE
DS3 NRZ I/O clock & data
Copyright 2001 TranS