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TC74HC595AFN - CMOS Digital Integrated Circuit Silicon Monolithic 8-Bit Shift Register/Latch

Download the TC74HC595AFN datasheet PDF. This datasheet also covers the TC74HC595AF variant, as both devices belong to the same cmos digital integrated circuit silicon monolithic 8-bit shift register/latch family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: fmax = 55 MHz (typ. ) at VCC = 5 V Low power dissipation: ICC = 4 μA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Output drive capability: 15 LSTTL loads for QA to QH 10 LSTTL loads for QH’ Symmetrical output impedance: |IOH| = IOL = 6 mA (min) For QA to QH |IOH| = IOL = 4 mA (min) For QH’ ∼ tpHL Balanced propagation delays: tpLH.
  • Wide operating voltage range: VCC (opr) = 2 to 6 V Pin and function compat.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HC595AF_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TC74HC595AFN
Manufacturer Toshiba
File Size 273.08 KB
Description CMOS Digital Integrated Circuit Silicon Monolithic 8-Bit Shift Register/Latch
Datasheet download datasheet TC74HC595AFN Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74HC595AP/AF/AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC595AP,TC74HC595AF,TC74HC595AFN 8-Bit Shift Register/Latch (3-state) The TC74HC595A is a high speed 8-BIT SHIFT REGISTER/LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The TC74HC595A contains an 8-bit static shift register which feeds an 8-bit storage register. Shift operation is accomplished on the positive going transition of the SCK input. The output register is loaded with the contents of the shift register on the positive going transition of the RCK www.DataSheet4U.com input. Since RCK and SCK signal are independent, parallel outputs can be held stable during the shift operation.