TMP92CF30FG Datasheet | Toshiba

Features The TMP92CF30 is a high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. The TMP92CF30FG is housed in a 176-pin QFP package. (1) CPU: 32-bit CPU (High-speed 900/H1 CPU) - patible with TLCS-900/L1 instruction code - 16 Mbytes of linear address space - General-purpose register and register banks - Micro DMA: 8channels (62.5 ns/4 bytes at f SYS = 80 MHz, best case) (2) Minimum instruction execution time : 12.5 ns (at f SYS = 80 MHz) (3) Internal RAM: 144 Kbytes (can be used for program and data) Internal ROM: None (4) External memory expansion - Expandable up to 2.1 Gbytes (shared program/data area) - Can simultaneously support 8-, 16- and 32-bit width external data buses …… Dynamic data bus sizing - Separate bus system (5) Memory controller - Chip select output: 4 channels - One channel in 4 channels is enabled detailed AC enable setting (6) 8-bit timers: 8 channels (7) 16-bit timer/event counter: 2 channels (8) General-purpose serial interface: 2 channels - UART/synchronous mode: 2 channels - Ir DA ver.1.0 (115.2 kbps) selectable (9) Serial bus interface: 1 channel - I2C standard mode only (10) USB (universal serial bus) controller: 1 channel - Full-speed (12 Mbps) (Low-speed is not supported.) - Endpoint 0: Control 64 bytes × 1 FIFO Endpoint 1: BULK (output) 64 bytes × 2 FIFOs Endpoint 2: BULK (input) 64 bytes × 2 FIFOs Endpoint 3: Interrupt (input) 8 bytes × 1 FIFO - Descriptor RAM: 384 bytes 92CF30-1 2009-06-12 TMP92CF30 (11) I2S (Inter-IC Sound) interface: 1 channel - I2S bus mode selectable (Master, transmission only) - Data Format is supported Left/Right Justify - 128-byte FIFO buffer (64 bytes × 2) (12) SDRAM controller:1 channel - Supports 16-Mbit, 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit SDR (Single-data-rate) SDRAM - Possible to execute instruction on SDRAM (13) Timer for real-time clock (RTC) - Based on TC8521A (14) Key-on wakeup (Interrupt key input) (15) 10-bit A/D converter (Built in Sample...