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TMP8156P - 2048-BIT STATIC MOS RAM

Download the TMP8156P datasheet PDF. This datasheet also covers the TMP8155P variant, as both devices belong to the same 2048-bit static mos ram family and are provided as variant models within a single manufacturer datasheet.

Description

The TMP 8155P/8156P are RAM including I/O ports and counter/timer on the chip for using in the TLCS-85A microcomputer system.

The RAM portion is designed with 2K bit static cells organized as 256 x 8.

The 14 bit programmable counter/ timer is the down counter.

Features

  • Compatible with Intel's 8155/8516 Single '+5 V Power Supply Access Time: 400 ns (MAX. ) Internal Address Latch 2 Programmable 8 Bit I/O Ports and 1 Programmable 6 Bit I/O Port. 256 Word x 8 Bits RAM Programmable 14 Bit Binary Counter/Timer Multiplexed Address and Data Bus Chip Enable Active High (TMP8l56P) or Low (TI!PS155P) 40 pin DIP PIN.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TMP8155P-Toshiba.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number TMP8156P
Manufacturer Toshiba
File Size 612.12 KB
Description 2048-BIT STATIC MOS RAM
Datasheet download datasheet TMP8156P Datasheet

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Other Datasheets by Toshiba

Part Number Description
TMP8155P 2048-BIT STATIC MOS RAM
TMP8022P 8-bit single chip microcomputer
TMP8035P 8-BIT SINGLE-CHIP MICROCOMPUTER
TMP8035PI 8-BIT SINGLE-CHIP MICROCOMPUTER
TMP8039P 8-BIT SINGLE-CHIP MICROCOMPUTER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
• INTEGRATEDCIRCUIT iii » TECHNICAL DATA TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT Tl'lP8155P TMP8156p N-CHANNEL SILICON GATE MOS 2048 BIT STATIC MOS RAM WITH I/O PORTS AND TIMER GENERAL DESCRIPTION The TMP 8155P/8156P are RAM including I/O ports and counter/timer on the chip for using in the TLCS-85A microcomputer system. The RAM portion is designed with 2K bit static cells organized as 256 x 8. The 14 bit programmable counter/ timer is the down counter. It provides either a square wave or terminal count pulse for the cpu system depending on timer mode. The I/O portion is consists of 2 programmable 8 bit I/O ports and 1 program~ mable 6 bit I/O port. The programmable I/O ports can be operated by BASIC MODE and STROBE MODE.