TMP8048PI Datasheet | Toshiba

FEATURES patible with Intel's 8048 2.5 w S Instruction Cycle All instruction 1 or 2 cycles Over- 90 instructions; 70% single byte Easy expandable memory and I/O l K x 8 masked ROM PIN CONNECTIONS (Top View) XTALl XTAL2 RESET SS INT EA RD PSEN WR ALE DBO DBI DB Z DB3 DB4 DBs DB6 DB7 (OV)VSS 64 x 8 RAM 27 I/O lines Interval Timer/Event Counter Single level interrupt Single SV supply -40'e to +85'e Operation (Tl1P8048PI/ TMP8035PI : Industrial Specification) Vce (+s V) Tl 1'27 P26 P2s P2I, P17 P16 PIS P14 P13 P12 Pll PIO VDD(+s V) PROG P 23 P22 P2l P20 - INTEGRATEDCIRCUIT TECHNICAL DATA BLOCK DIAGRAM Oscillation Frequency TMP8048P/8048PI H1P8035P/8035PI 2 Mask ROM l K x 8 (Program Area) gister/ Decoder 1====:::;-, Accumula tor Bit Test 6 RAM 64 x 8 Control and Timing Circuit XTAL z XTAL1 RESET INT EA SS ALE PSEN ill WR PROG ".Hg '","... rt H '" H III .0r.,t '" " "~...