Datasheet4U Logo Datasheet4U.com

TC74VHC9164FK - 8-Bit Shift Register

Key Features

  • High speed: fmax  149 MHz (typ. ) at VCC  5 V.
  • Low power dissipation: ICC  4 A (max) at Ta  25°C.
  • Power down protection is provided on all inputs.
  • Balanced propagation delays: tpLH tpHL.
  • Wide operating voltage range: VCC (opr)  2 to 5.5 V © 2018 1 Toshiba Electronic Devices & Storage Corporation Start of commercial production 2011-03 2018-06-22 Pin Assignment TC74VHC9164FK P/S CONT 1 2 SI 3 CK 4 Q/D1 5 Q/D2 6 Q/D3 7 GND 8 (top view) t 16 VCC 15 Q8C 14.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
TC74VHC9273FK Octal D-Type Flip-Flop Toshiba Semiconductor
TC74VHC9273FT CMOS Digital Integrated Circuit Silicon Monolithic Toshiba Semiconductor
TC74VHC9273P Octal D-Type Flip-Flop Toshiba Semiconductor
TC74VHC9541FK Octal Universal Schmitt Buffer Toshiba Semiconductor
TC74VHC9541FT Octal Universal Schmitt Buffer Toshiba Semiconductor

Other Datasheets by Toshiba

Part Number Description
TC74VHC9125P 5-bit Universal Schmitt Buffer
TC74VHC9126FK 5-bit Universal Schmitt Buffer
TC74VHC9126P 5-bit Universal Schmitt Buffer
TC74VHC912FK 5-bit Universal Schmitt Buffer
TC74VHC9151FK 9-Bit Schmitt Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74VHC9164FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC9164FK 8-Bit Shift Register (Parallel-IN/ Serial-OUT, Serial -IN/ Parallel -OUT) The TC74VHC9164 is an ultra-high-speed 8-Bit Shift Register fabricated using silicon-gate CMOS technology. The TC74VHC9164 combines low power consumption of CMOS with Schottky TTL speeds. The TC74VHC9164 has parallel data inputs/outputs, a serial input and a serial output. It converts parallel data into serial data or vice versa. When P/S CONT is Low, Q/D1 to Q/D8 are configured as parallel data outputs. At this time, the SI input is serially loaded on the rising edges of CK and unloaded from the Q/D1 to Q/D8 outputs in parallel. When CLR/LOAD input is Low, all flip-flops are asynchronously reset, irrespective of the CK state.