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TC74VHC153FK - Dual 4-Channel Multiplexer

Download the TC74VHC153FK datasheet PDF. This datasheet also covers the TC74VHC153F variant, as both devices belong to the same dual 4-channel multiplexer family and are provided as variant models within a single manufacturer datasheet.

Features

  • High speed: tpd = 5.0 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Power down protection is provided on all inputs.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 5.5 V.
  • Pin and function compatible with 74ALS153 TC74VHC153F TC74VHC153FK Weight SOP16-P-300-1.27A VSSOP16-P-0030-0.50 : 0.18 g (typ. ) : 0.02 g (typ. ) © 2019 1.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74VHC153F_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
TC74VHC03F Quad 2-Input NAND Gate Toshiba Semiconductor
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TC74VHC03FT Quad 2-Input NAND Gate Toshiba Semiconductor
TC74VHC9273FK Octal D-Type Flip-Flop Toshiba Semiconductor

Other Datasheets by Toshiba

Part Number Description
TC74VHC153F Dual 4-Channel Multiplexer
TC74VHC153FN DUAL 4-CHANNEL MULTIPLEXER
TC74VHC153FS DUAL 4-CHANNEL MULTIPLEXER
TC74VHC153FT DUAL 4-CHANNEL MULTIPLEXER
TC74VHC157F Quad 2-Channel Multiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74VHC153F/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC153F, TC74VHC153FK Dual 4-Channel Multiplexer The TC74VHC153 is an advanced high speed CMOS DUAL 4CHANNEL MULTIPLEXERs fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Each of these data (1C0-1C3, 2C0-2C3) is selected by the two address inputs A and B. Separate strobe inputs (1G , 2G ) are provided for each of the two fourline sections. The strobe input ( G ) can be used to inhibit the data output; the output is fixed in low level while the strobe input is held high. An input protection circuit ensures that 0 to 5.
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