TC74HC40102AF, TC74HC40102AP Datasheet - Toshiba

TC74HC40102AF Dual BCD Programmable Down Counter

Count Inhibit Count is inhibited regardless of other inputs. Regular Count Down count on the rising edge of CK Synchronous Preset Input data is preset on the rising edge of CK Asynchronous Preset Input data is asynchronously preset to CK Clear Counter is set to maximum count. X: Don’t care M.

TC74HC40102,40103AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC40102AP, TC74HC40102AF TC74HC40103AP, TC74HC40103AF TC74HC40102AP/AF Dual BCD Programmable Down Counter TC74HC40103AP/AF 8-Bit Binary Programmable Down Counter The TC74HC40102A and TC74HC40103A are high speed CMOS PROGRAMMABLE DOWN COUNTERS fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The ou.

TC74HC40102AF Features

* High speed: fmax 40 MHz (typ.) at VCC = 5 V

* Low power dissipation: ICC = 4 μA (max) at Ta = 25°C

* High noise immunity: VNIH = VNIL = 28% VCC (min)

* Output drive capability: 10 LSTTL loads

* Symmetrical output impedance: |IOH| = IOL = 4 mA (min)

TC74HC40102AP-Toshiba.pdf