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TC74HC138AP - 3-TO-8 Line Decoder

Download the TC74HC138AP datasheet PDF. This datasheet also covers the TC74HC138 variant, as both devices belong to the same 3-to-8 line decoder family and are provided as variant models within a single manufacturer datasheet.

Features

  • High speed: tpd = 16 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability:.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HC138_Toshiba.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Toshiba

Part Number Description
TC74HC138AF 3-TO-8 Line Decoder
TC74HC138AFN 3-TO-8 Line Decoder
TC74HC132AF QUAD 2-INPUT SCHMITT GATE
TC74HC132AFN QUAD 2-INPUT SCHMITT GATE
TC74HC132AP QUAD 2-INPUT SCHMITT GATE

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74HC138AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC138AP, TC74HC138AF 3-to-8 Line Decoder The TC74HC138A is a high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems.
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