TC55V328J-25 Datasheet, Toshiba

low power dissipation when the SRAM is deselected using chip enable (CE) and has an output enable input (OE) for fast memory access. It is suitable for use in high speed .

such as cache memory. All inputs and outputs are LVTTL (low voltage TIL) compatible. The TC55V328J is available in a 28-.

The TC55V328J is a 262,144 bit CMOS high speed static random access memory organized as 32,768 words by 8 bits and designed to operate from a single 3.3V supply. Toshiba's advanced CMOS technology and circuit design enable high speed, low voltage op.

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