low power dissipation when the device is deselected using chip enable (CE1, CE2) and has an output enable input (OE) for fast memory access. Also, the device power betwee.

uch as cache memory and high speed storage. All inputs and outputs are TIL compatible. The TC5589P/J is available in a 3.

The TC5589P/J is a 73,728 bit high speed CMOS static random access memory organized as 8,192 words by 9 bits and operated from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable high speed~ration. The TC5589P/J features.

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