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TC554101J-25 - 4-Bit Separate I/O CMOS SRAM

Download the TC554101J-25 datasheet PDF. This datasheet also covers the TC554101J-20 variant, as both devices belong to the same 4-bit separate i/o cmos sram family and are provided as variant models within a single manufacturer datasheet.

Description

The TC5541 01 J is a 4,194,304 bit high speed CMOS static random access memory organized as 1,048,576 words by 4 bits and operated from a single 5V supply.

Toshiba's advanced CMOS technology and circuit design enable hi~peed operation.

Features

  • low power dissipation when the device is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. The TC5541 01 J is suitable for use in.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC554101J-20-Toshiba.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TOSHIBA 112554101]-20/25/30 SILICON GATE CMOS 1,048,576 WORD x 4 BIT SEPARATE 1/0 CMOS STATIC RAM PRELIMINARY Description The TC5541 01 J is a 4,194,304 bit high speed CMOS static random access memory organized as 1,048,576 words by 4 bits and operated from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable hi~peed operation. The TC5541 01 J features low power dissipation when the device is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. The TC5541 01 J is suitable for use in applications where high speed is required such as cache memory, high speed storage, and main memory. All inputs and outputs are TTL compatible.
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