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TC551402J-20 - CMOS SRAM

Description

The TC551402J is a 4,194,304 bit high speed CMOS static random access memory that is configurable to an organization of either 4,194,304 words by 1 bit or 1,048,576 words by 4 bits when power is initially applied to the device.

The mode (x1/x4) is selected by the input level of pin 17 (81/84).

Features

  • low power dissipation when the SRAM is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. It is suitable for use in high speed.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TOSHIBA 11:551402J-20/25/30 4,194,304 WORD x 1 BIT/1,048,576 WORD x 4 BIT CMOS STATIC RAM Description The TC551402J is a 4,194,304 bit high speed CMOS static random access memory that is configurable to an organization of either 4,194,304 words by 1 bit or 1,048,576 words by 4 bits when power is initially applied to the device. The mode (x1/x4) is selected by the input level of pin 17 (81/84). The TC551402J operates from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable high speed operation. The TC551402J features low power dissipation when the SRAM is deselected using chip enable (CE), and has an output enable input (OE) for fast memory access. It is suitable for use in high speed applications such as cache memory, high speed storage, and main memory.
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