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TC518512FL-10DR - SILICON GATE CMOS PSEUDO STATIC RAM

Download the TC518512FL-10DR datasheet PDF. This datasheet also covers the TC518512PL-70DR variant, as both devices belong to the same silicon gate cmos pseudo static ram family and are provided as variant models within a single manufacturer datasheet.

Description

The TC518512PL is a 4M bit high speed CMOS pseudo static RAM organized as 524,288 words by 8 bits.

The TC518512PL utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, .!J!gh speed and low power storage.

Features

  • a static RAM-like interface with a write cycle in which the input data is written into the memory cell at the rising edge of RNV thus simplifying the microprocessor interface. The TC518512PL is available in a 32-pin, 0.6 inch width plastic DIP, a small outline plastic flat package, and a thin small outline package (forward type, reverse type). Features.
  • Organization: 524,288 words x 8 bits.
  • Single 5V p.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC518512PL-70DR-Toshiba.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
rOSHIBA TC518512PL/FL/FIL/TRL-70(DR) /80 (DR) /10 (DR) SILICON GATE CMOS 524,288 WORD x 8 BIT CMOS PSEUDO STATIC RAM Description The TC518512PL is a 4M bit high speed CMOS pseudo static RAM organized as 524,288 words by 8 bits. The TC518512PL utilizes a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, .!J!gh speed and low power storage. The TC518512PL operates from a single 5V power supply. Refreshing is supported by a refresh (OEIRFSH) input which enables two types of refreshing - auto refresh and self refresh. The TC518512PL features a static RAM-like interface with a write cycle in which the input data is written into the memory cell at the rising edge of RNV thus simplifying the microprocessor interface.
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