TC358766XBG
Overview
- Translates MIPI® DSI/DPI Link video stream from Host to DisplayPortTM Link data to external display devices.
- The inputs are driven by a DSI Host with 4-Data Lanes, upto1 Gbps/lane or DPI Host with 16/18/24 bit interface upto154 MHz parallel clock.
- Supports HDCP Digital Content Protection version 1.3 (DisplayPortTM amendment Rev1.1).
- The output Interface consists of a DisplayPortTM Tx with a 2-lane Main Link and AUX-Ch.
- Register Configuration: From DSI link, SPI or I2C interface (only one of the SPI and I2C interfaces can be active at any time).
- Internally generated H/VSync in DSI mode can be muxed out to Host.
- Interrupt to host to inform any error status or status needing attention from Host.
- Internal test pattern (color bar) generator for DP o/p testing without any video (DSI/DPI) i/p.
- Debug/Test Port: I2C Slave
- DSI Receiver: Supports one DSI Interface between TC358766XBG and Host. MIPI® DSI: v1.01 / MIPI® D-PHY: v0.90 Compliant. Up to four (4) Data Lanes with Bi-direction support on Data Lane 0. Maximum speed at 1 Gbps/lane. Supports Burst as well as Non-Burst Mode Video Data. - Video data packets are limited to one row per Hsync period. Supports video stream packets for video data transmission. Supports generic long packets for accessing the chip’s register set. Video input data formats: - RGB-565, RGB-666 and RGB-888. - New DSI V1.02 Data Type Support: 16-bit YCbCr 422 Interlaced video mode is not supported.
