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74VHC138FT - 3-to-8 Line Decoder

Description

2.

The 74VHC138FT is an advanced high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology.

It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.

Features

  • (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature: Topr = -40 to 125  (3) High speed: tpd = 5.7 ns (typ. ) at VCC = 5 V (4) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  (5) High noise immunity: VNIH = VNIL = 28 % VCC (min) (6) Power down protection is provided on all inputs. (7) Balanced propagation delays: tPLH ≈ tPHL (8) Wide operating voltage range: VCC(opr) = 2.0 V to 5.5 V (9) Pin and function compatible with 74 series(AC/HC/AHC/LV etc. )138 type. Note 1: This device is.

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Full PDF Text Transcription

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CMOS Digital Integrated Circuits Silicon Monolithic 74VHC138FT 74VHC138FT 1. Functional Description • 3-to-8 Line Decoder 2. General The 74VHC138FT is an advanced high speed CMOS 3-to-8 DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems. An input protection circuit ensures that 0 to 5.
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