18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS
SCES187D – JANUARY 1999 – REVISED JULY 2005
• Members of the Texas Instruments Widebus™
• Universal Bus Transceiver (UBT™) Combines
D-Type Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, Clocked,
or Clock-Enabled Modes
• Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
• Support Mixed-Mode (3.3-V and 5-V) Signal
Operation on A-Port and Control Inputs
• B-Port Transition Time Optimized for
Distributed Backplane Loads
• Ioff Supports Partial-Power-Down Mode
• Bus Hold on A-Port Inputs Eliminates the
Need for External Pullup/Pulldown Resistors
• Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline
(DGG), and Ceramic Flat (WD) Packages
The 'GTL16612A devices are 18-bit universal bus transceivers (UBT) that provide LVTTL-to-GTL+ and
GTL+-to-LVTTL signal-level translation. They allow for transparent, latched, clocked, or clock-enabled modes of
data transfer. These devices provide a high-speed interface between cards operating at LVTTL logic levels and
backplanes operating at GTL+ signal levels. High-speed (about two times faster than standard LVTTL or TTL)
backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and
output edge control (OEC™). Improved GTL+ OEC circuits minimize bus settling time and have been designed
and tested using several backplane models.
Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is a
16-slot, 14-inch board with loaded impedance of 33 Ω. VTT is 1.5 V, VREF is 1 V, and RTT pullup resistor is 50 Ω.
The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot-1 signals are
shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing
between receiver cards is reduced. The clock is independent of the data, and the system clock frequency is
limited by the backplane flight time to about 80-90 MHz. This frequency can be increased even more (30% to
40%) if the clock is generated and transmitted together with the data from the driver card (source synchronous).
t − Time − ns
Figure 1. Test Backplane Model With Output Waveform Results
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.