900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Texas Instruments (TI) Electronic Components Datasheet

SN74GTL16612A Datasheet

18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers

No Preview Available !

www.ti.com
SN54GTL16612A, SN74GTL16612A
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS
SCES187D – JANUARY 1999 – REVISED JULY 2005
FEATURES
Members of the Texas Instruments Widebus™
Family
Universal Bus Transceiver (UBT™) Combines
D-Type Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, Clocked,
or Clock-Enabled Modes
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
Support Mixed-Mode (3.3-V and 5-V) Signal
Operation on A-Port and Control Inputs
B-Port Transition Time Optimized for
Distributed Backplane Loads
Ioff Supports Partial-Power-Down Mode
Operation
Bus Hold on A-Port Inputs Eliminates the
Need for External Pullup/Pulldown Resistors
Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink Small-Outline
(DGG), and Ceramic Flat (WD) Packages
xxx
DESCRIPTION
The 'GTL16612A devices are 18-bit universal bus transceivers (UBT) that provide LVTTL-to-GTL+ and
GTL+-to-LVTTL signal-level translation. They allow for transparent, latched, clocked, or clock-enabled modes of
data transfer. These devices provide a high-speed interface between cards operating at LVTTL logic levels and
backplanes operating at GTL+ signal levels. High-speed (about two times faster than standard LVTTL or TTL)
backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and
output edge control (OEC™). Improved GTL+ OEC circuits minimize bus settling time and have been designed
and tested using several backplane models.
Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is a
16-slot, 14-inch board with loaded impedance of 33 . VTT is 1.5 V, VREF is 1 V, and RTT pullup resistor is 50 .
The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot-1 signals are
shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing
between receiver cards is reduced. The clock is independent of the data, and the system clock frequency is
limited by the backplane flight time to about 80-90 MHz. This frequency can be increased even more (30% to
40%) if the clock is generated and transmitted together with the data from the driver card (source synchronous).
VTT
0.25”
0.875”
VTT
0.25”
1.8
1.6
TI GTL16612
0.625”
0.625”
0.625”
0.625”
1.4
1.2
Fairchild GTLP16612
Conn.
1”
Rcvr
Slot 1
Conn.
Conn.
Conn.
1.0
1”
Rcvr
Slot 2
1”
Drvr
Slot 8
1”
Rcvr
Slot 16
0.8
0.6
0.4
0
TI GTL16612A
10 20
t − Time − ns
Figure 1. Test Backplane Model With Output Waveform Results
30
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.


Texas Instruments (TI) Electronic Components Datasheet

SN74GTL16612A Datasheet

18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers

No Preview Available !

SN54GTL16612A, SN74GTL16612A
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS
SCES187D – JANUARY 1999 – REVISED JULY 2005
www.ti.com
DESCRIPTION (CONTINUED)
Additional design considerations can be found in Application Information at the end of this data sheet.
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in
transparent, latched, clocked, and clock-enabled modes. These UBTs can replace any of the functions shown in
Table 1.
Table 1. 'GTL16612A UBT Replacement Functions
FUNCTION
Transceiver
Buffer/driver
Latched transceiver
Latch
Registered transceiver
Flip-flop
Standard UBT
Universal bus driver
Registered transceiver with CLK enable
Flip-flop with CLK enable
Standard UBT with CLK enable
8 BIT
'245, '623, '645
'241, '244, '541
'543
'373, '573
'646, '652
'374, '574
9 BIT
'863
'843
10 BIT
'861
'827
'841
'821
16 BIT
'16245, '16623
'16241, '16244, '16541
'16543
'16373
'16646, '16652
'16374
'2952
'377
'823
'GTL16612A UBT replaces all above functions
'16470, '16952
18 BIT
'16863
'16825
'16472
'16843
'16474
'16500, '16501
'16835
'16823
'16600, '16601
xxx
GTL+ is the Texas Instruments (TI™) derivative of the Gunning transceiver logic (GTL) JEDEC standard
JESD 8-3. The AC specification of the 'GTL16612A is given only at the preferred higher noise margin GTL+, but
this device can be used at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V and VREF = 1 V)
signal levels.
The B port normally operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with
LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port.
To improve signal integrity, the 'GTL16612A B-port output transition time is optimized for distributed backplane
loads.
VCC (5 V) supplies the internal and GTL circuitry, while VCC (3.3 V) supplies the LVTTL output buffers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock or latch enable can be controlled by the clock-enable (CEAB
and CEBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low,
the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB
is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B
to A is similar to that for A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
The SN54GTL16612A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74GTL16612A is characterized for operation from –40°C to 85°C.
2


Part Number SN74GTL16612A
Description 18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers
Maker Texas
Total Page 15 Pages
PDF Download

SN74GTL16612A Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 SN74GTL16612 18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers (Rev. K)
Texas Instruments
2 SN74GTL16612A 18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers
Texas





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy