17ĆBIT TTL/BTL UNIVERSAL STORAGE TRANSCEIVER
WITH BUFFERED CLOCK LINE
SCBS177O − OCTOBER 1993 − REVISED MARCH 2004
The SN74FB1651 contains an 8-bit and 9-bit transceiver with a buffered clock. The clock and the transceivers
are designed to translate signals between TTL and backplane transceiver-logic (BTL) environments. The
device is designed specifically to be compatible with IEEE Std 1194.1-1991.
The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA. Two output
enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC is less than 2.1 V,
the B port is turned off.
The A port operates at TTL-signal levels. The A outputs reflect the inverse of the data at the B port when the
A-port output enable (OEA) is high. When OEA is low or when VCC is less than 2.1 V, the A outputs are in the
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
BG VCC and BG GND are the supply inputs for the bias generator.
0°C to 70°C TQFP − PCA Tube
† Package drawings, standard packing quantities, thermal data, symbolization, and
PCB design guidelines are available at www.ti.com/sc/package.
A data to B bus
B data to A bus
A data to B bus, B data to A bus
H X Transparent
L ↑ Store data
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